export path_tb = ${VERI_HOME}
GROUP_NAME    ?= sanity
C_TEST_DIR    ?= ${path_tb}/fw/tests
C_TEST        ?= 
UVM_TEST      ?= uvm_base_test
RTL_FILELIST  ?= ${path_tb}/group_list/$(GROUP_NAME)/rtl.f
TB_FILELIST   ?= ${path_tb}/group_list/$(GROUP_NAME)/tb.f
VIP_FILELIST  ?= ${path_tb}/group_list/$(GROUP_NAME)/vip.f
TCL_FILE      ?= ${path_tb}/tcl/base_run.tcl
FSDB_DUMP     ?= on
COVERAGE      ?= off
COVERAGE_TYPE ?= line+branch+cond+tgl+fsm
GATE_SIM      ?= off
SEED          ?= 1
COV_DIR       ?= ${path_tb}/sim/cov
TB_TOP        ?= TestbenchTop
SIM_ARGS      ?= 
RTL_COMP_OPTS ?=
VIP_COMP_OPTS ?=
TB_COMP_OPTS  ?=
ELAB_COMP_OPTS  ?=
CTFLAGS     ?=
UVM_TIMEOUT   ?=1000000
TIME_SCALE    ?=1ns/10ps
UVM_VERBOSITY ?= UVM_DEBUG
## get all include path
CC=gcc
CXX=g++
C_OPT= -fPIC -std=c++11 -g -w
C_INCLUDE=-I${VCS_HOME}/include -I${path_tb}/tb/c_dpi 
C_DEF_ARGS=-DVCS 
INCLUDE_PATH := $(path_tb)/fw/lib/include
INCLUDE_PATH += $(VCS_HOME)/etc/uvm/dpi
INCLUDE_PATH += $(path_tb)/fw/lib/src/uvm
INCLUDE_PATH += $(path_tb)/fw/lib/src/
INCLUDE_PATH += $(path_tb)/tb/c_dpi
INCLUDE_PATH += $(C_TEST_DIR)/$(C_TEST)
SRC_PATH  := $(path_tb)/fw/lib
SRC_PATH  += $(path_tb)/tb/c_dpi/
SRC_PATH += $(path_tb)/fw/lib/src/
SRC_PATH += $(path_tb)/fw/lib/src/uvm
SRC_PATH += $(C_TEST_DIR)/$(C_TEST)

CFLAGS  += $(foreach dir,$(INCLUDE_PATH), $(foreach sub_dir, $(wildcard $(dir)), -I$(sub_dir)))
CFLAGS  += $(CTFLAGS)
SRCS += $(foreach dir, $(SRC_PATH), $(wildcard $(dir)/*.c))
OBJ = ${patsubst %.c, %.o, $(SRCS)}
SIM_DIR ?=
COMP_DIR ?=

#-timescale=1ns/1ps -ntb_opts tb_timescale=1ns/1ps
ifeq ($(COVERAGE), on)
COVERAGE_OPTS = -cm_dir $(COV_DIR) -cm $(COVERAGE_TYPE)
else
COVERAGE_OPTS = 
endif

export MY_FSDB_DUMP=$(FSDB_DUMP)
#MODEL_DEBUG_OPT=+define+DEBUG_EN=1 +define+MODEL_DEBUG_MEMORY +define+MODEL_DEBUG_CMDS 

.PHONY : comp elab sim c_comp regression rtl_update env_check prepare_comp_dir prepare_sim_dir help log clean debug  cover_merge verdi_cov

ifneq ( $(QUITE_MODE), 0)
QUITE_OPTS = > /dev/null 
QUITE=@
else
QUITE_OPTS= 
QUITE=
endif
help:
	@echo "---------------------------------------------------------------"
	@echo "      make clean                          | Clean the compile directory"
	@echo "      make list                           | List the available Tests Names"
	@echo "      make comp  TEST=<Your TEST NAME>    | Compile the rtl and test bench code"
	@echo "      make sim   TEST=<Your TEST NAME>    | Run you specified simulation"
	@echo "      make verdi TEST=<Your TEST NAME>    | Open the RTL code & waveform with verdi"
	@echo "      make log   TEST=<Your TEST NAME>    | gvim open the simulation log"
	@echo "---------------------------------------------------------------"

env_check:
	@echo "---------------------------------------------------------------"
	@echo "      Check the enviornment"
ifdef RTL_ROOT
	@echo "         RTL_ROOT      = ${RTL_ROOT}"
else
	$(error environment variable $${RTL_ROOT} not defined)
endif
#--------------------------------------------------------
#CD to HIPU200 RTL Directory & Update GIT based rtl code
#--------------------------------------------------------
rtl_update: env_check
	cd ${path_tb}; git pull

prepare_cov_dir:
	$(if $(wildcard $(COV_DIR)),,mkdir -p $(COV_DIR))

prepare_comp_dir:
	$(if $(wildcard $(COMP_DIR)),,mkdir -p $(COMP_DIR))

prepare_sim_dir:
	$(if $(wildcard $(SIM_DIR)),,mkdir -p $(SIM_DIR))

ifeq ($(GATE_SIM), on)
else
comp: prepare_comp_dir comp_rtl comp_vip comp_tb elab

comp_rtl: 
	cd $(COMP_DIR); \
	vlogan -ntb_opts uvm-1.2 -full64 -error=noMPD -l comp_rtl.log -sverilog  \
			+lint=TFIPOC-L +lint=PCWM \
			+vc -lca -debug_access+all \
			+notimingcheck  \
			+error+100\
            -kdb \
           	$(TB_DEF_OPTS) \
           	$(RTL_COMP_OPTS) \
			-file $(RTL_FILELIST)  

comp_vip: 
	cd $(COMP_DIR); \
	vlogan -ntb_opts uvm-1.2 -full64 -error=noMPD -l comp_uvm.log -sverilog \
			+lint=TFIPOC-L +lint=PCWM \
			+vc -lca -debug_access+all \
			+error+100\
            -kdb \
           	$(TB_DEF_OPTS) \
           	$(VIP_COMP_OPTS); \
	cd $(COMP_DIR); \
	vlogan -ntb_opts uvm-1.2 -full64 -error=noMPD -l comp_vip.log -sverilog \
			+lint=TFIPOC-L +lint=PCWM \
			+vc -lca -debug_access+all \
			+error+100\
            -kdb \
           	$(TB_DEF_OPTS) \
           	$(VIP_COMP_OPTS) \
			-file $(VIP_FILELIST) 

comp_tb: 
	cd $(COMP_DIR); \
	vlogan -ntb_opts uvm-1.2 -full64 -error=noMPD -l comp_tb.log -sverilog \
			+lint=TFIPOC-L +lint=PCWM \
			+vpi \
			+vc -lca  -debug_access+all \
			+error+100\
            -kdb \
           	$(TB_DEF_OPTS) \
           	$(TB_COMP_OPTS) \
			-timescale=$(TIME_SCALE)\
			-file $(TB_FILELIST) 

elab:
	cd $(COMP_DIR); \
	vcs -ntb_opts uvm-1.2 -full64 -error=noMPD -l vcs.log -sverilog \
			+lint=TFIPOC-L +lint=PCWM \
			+vc -lca -j4 -debug_access+all \
			+notimingcheck +nospecify \
			+error+100\
            -kdb \
            -top $(TB_TOP)  \
           	$(TB_DEF_OPTS) \
			-timescale=$(TIME_SCALE)\
			$(ELAB_COMP_OPTS)\
			$(COVERAGE_OPTS) 
			
endif

	#-cm line+branch+cond+tgl+fsm -cm_dir $(COV_DIR)/$(TEST)_$(SEED) 
	#+LINK_UP_SPEED_GEN1 

ifeq ($(GATE_SIM), on)
else
ifeq ($(C_TEST), )
sim: prepare_sim_dir
	$(QUITE)cd $(SIM_DIR); \
	$(COMP_DIR)/simv \
	-l sim.log \
	+UVM_VERBOSITY=$(UVM_VERBOSITY) \
  	+UVM_TESTNAME=$(UVM_TEST) +UVM_NO_RELNOTES \
	+UVM_TIMEOUT=$(UVM_TIMEOUT) \
	+fsdb+delta \
    $(COVERAGE_OPTS) \
	+RANDOM_SEED=$(SEED)  +ntb_random_seed=$(SEED)\
	$(SIM_ARGS) \
	$(TCL_FILE) -ucli -do $(TCL_FILE) \

else
sim: prepare_sim_dir test.so
	$(QUITE)cd $(SIM_DIR); \
	$(COMP_DIR)/simv \
	-l sim.log \
	-sv_lib ${C_TEST_DIR}/${C_TEST}/test \
	-l sim.log \
	+UVM_VERBOSITY=$(UVM_VERBOSITY) \
  	+UVM_TESTNAME=$(UVM_TEST) +UVM_NO_RELNOTES \
	+fsdb+all \
	$(SIM_ARGS) \
    $(COVERAGE_OPTS) \
	+RANDOM_SEED=$(SEED)  +ntb_random_seed=$(SEED)\
	$(TCL_FILE) -ucli -do $(TCL_FILE) \

endif
endif

log:
	gvim $(SIM_DIR)/sim.log


verdi: env_check
	cd $(COMP_DIR);\
	verdi -dbdir simv.daidir -ssf $(SIM_DIR)/tb.vf &
	
rtl_verdi: env_check
	cd $(SIM_DIR);\
	verdi -error=noMPD -l comp.log -sverilog +delay_mode_distributed +define+DWC_ADD_PHY_DELAY +define+SIM +define+DEBUG_EN=0 $(MODEL_DEBUG_OPT) \
			-timescale=1ns/1ps -ntb_opts uvm-1.2 +lint=TFIPOC-L +lint=PCWM +vc -lca -top TestbenchTop +notimingcheck +nospecify \
			-f $(RTL_FILELIST) -f $(VIP_FILELIST) -f $(TB_FILELIST) -ssf $(SIM_DIR)/tb.vf &

clean:
	rm -rf $(COMP_DIR)

list:
	@echo "---------------------------------------------------------------"
	@echo "The Valid Tests are as Followins:"
	@echo "---------------------------------------------------------------"
	@ls -r -1 $(C_TEST_DIR) | pr -t --indent=10
	@echo "---------------------------------------------------------------"

test.so: $(SRCS)
	echo $(SRC_PATH);\
	cd $(C_TEST_DIR)/$(C_TEST);\
	rm -f test.so;\
	$(CC) $(C_OPT) $(C_DEF_ARGS) $(C_INCLUDE) $(CFLAGS) $(SRCS) -shared -o test.so

debug:
	@echo $(CFLAGS)
	@echo $(SRCS)
	@echo $(OBJ)

cov_merge:
	urg -full64 -dir $(COMP_DIR)/simv.vdb -dir $(COV_DIR)/*.vdb -format both -dbname cov_merge

verdi_cov: env_check
	dve -full64 -cov -dir cov_merge.vdb &
